Contents

  1. SystemC Books I have
  2. messages from web

1. SystemC Books I have

2. messages from web

Tenison VTOC is one well established tool, which achieves high performance of the resulting SystemC by raising the level of abstraction above the original RTL. Tenison provides free evaluation and has an academic support program.

why do we need SystemC language? 

I only know SystemC is a language that can be used to facilitate system verification. And I am told that it can be converted into HDL. Can SystemC do everything that Verilog/VHDL can do? Will it replace them completely? Thanks!


system c is both a HVL and HDL. it can support system discription and rtl discription, so in some sense, you can think it can do everything that verilog/vhdl can do.

but i don't think it will replace them, because
1. it can not support rtl discription as efficient as verilog/vhdl, i think.
2. some other hvl languages are competing with systemC now, such as system verilog, open vera, and e. which one will win is still a problem.


Initially, idea behind systemC was: 1 language for everything hardware, verification and software.
Today, it is clear that no company made synthesis tool with SystemC support.
Still , even without usage in hardware description, SystemC has big advantage over SystemVerilog in SW/HW co-design and co-verification, SW/HW partitioning.
Also, iteration between different arhitectures is much faster in SystemC then in any HDL.
Todays simulator (for example cadence nc-verilog plus nc_systemc) have support for systemc/HDL cosimulation. That means great simplification and speed up in block level verification environments (developing of full model in SystemC and replacement of only 1 module with HDL description).
For system arhitects, SoC integrators (especially if there are some embedded processors there, and in average there are few of thrm in each SoC today), verification engeneers, even for design engeneers who want to have proper executabile specification before any HDL coding, SystemC is the language of choise.
I still want to see synthesis tool with SystemC support - that means very smooth iterations between various C++/SystemC models only with no discontinuitet.


SystemC is supposed to do what VHDL/Verilog do .. Yet, the main problem is that it's not supported by synthesis tools .. Dunno y !! ..

The advantages of SystemC over normal HDLs are:

1- It can support System Level Description and RTL, both.
2- It is executable, which means u can use it to communicate between design teams (like between Software Team and Hardware Team) without being annoyed by those guys don't know how to interprete what others say .. and overcome the background flavor of the various engineers.
3- You can still use the same code written for the system description in RTL description with the use of the normal C++ features (like overloading, overriding, inheretance, etc.)
4- It supports both SW and HW simulation simultaneously without any need to partition ur design from the very begining.
5- You can use any C/C++ statement inside the code, and this makes it more likely to spread among engineers because most of the engineers know C/C++.
6- SystemC comes with some ready examples and packages that are extremely useful for design .. something like IPs.
7- It's completely for free and u can use it on GCC. This makes it cheaper than VHDL and Verilog cuz if u go for HDL u need a simulator .. and most of those simulators are not for free.

When you use VCS to cosim SystemC with Verilog, don't forget to source $VCS_HOME/vg_gnu_package/2005.06/linux/source_me.csh